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-- Company: 
-- Engineer: 
-- 
-- Create Date:    23:03:36 10/09/2013 
-- Design Name: 
-- Module Name:    Dem100 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Dem100 is
		Port(	
				CLK : in  STD_LOGIC;
				RESET : in  STD_LOGIC;				
				DIR : in  STD_LOGIC;
				Q0 : out STD_LOGIC_VECTOR(3 DOWNTO 0);
				Q1 : out STD_LOGIC_VECTOR(3 DOWNTO 0);
				FLAG : out  STD_LOGIC);
end Dem100;

architecture Behavioral of Dem100 is
	signal U: STD_LOGIC;
	component Dem10 is
		port( 
				CLK : in  STD_LOGIC;
				RESET : in  STD_LOGIC;				
				DIR : in  STD_LOGIC;
				Q : out STD_LOGIC_VECTOR(3 DOWNTO 0);
				FLAG : out  STD_LOGIC);
	end component;
	--component flagmux is
		--port( 
			--	CLK : in  STD_LOGIC;
			--	U : in std_logic;
			--	O: out STD_LOGIC);
	--end component;
begin
		DonVi: Dem10 port map (DIR => DIR, RESET => RESET, CLK => CLK, Q => Q0, FLAG => U);
		--FL: flagmux port map ( CLK => CLK, U => U, O => O);
		Chuc:  Dem10 port map (DIR => DIR, RESET => RESET, CLK => U, Q => Q1, FLAG => FLAG);
end Behavioral;

